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Da ta S h ee t, D S 1, N ov . 20 01
T - S M I NT O 4B3 T S e co n d G e n . M od ul ar I S D N N T ( O r din a ry )
PEF 80902 Version 1.1
Wired C o m m u n i ca t i o n s
Never stop thinking.
Edition 2001-11-12 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Da ta S h ee t, D S 1, N ov . 20 01
T - S M I NT O 4B3 T S e co n d G e n . M od ul ar I S D N N T ( O r din a ry )
PEF 80902 Version 1.1
Wired C o m m u n i ca t i o n s
Never stop thinking.
PEF 80902 Revision History: Previous Version: Page 2001-11-12 Preliminary Data Sheet 06.01 Subjects (major changes since last revision) DS 1
Table 10 Additional C/I-command LTD Figure 12 Chapter 2.3.7.4 Chapter 4.2 Chapter 4.4 Input Leakage Current AIN, BIN: max. 30A Reduced power consumption
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com
PEF 80902
Table of Contents 1 1.1 1.2 1.3 1.4 1.5 1.6 1.6.1 1.7 2 2.1 2.2 2.2.1 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.4.1 2.3.5 2.3.6 2.3.7 2.3.7.1 2.3.7.2 2.3.7.3 2.3.7.4 2.3.7.5 2.3.7.6 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.5.1 3 3.1 3.1.1 3.1.2 3.1.3 3.1.4
Data Sheet
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Not Supported are ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Specific Pins and Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4B3T Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maintenance Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coding from Binary to Ternary Data . . . . . . . . . . . . . . . . . . . . . . . . . . . Decoding from Ternary to Binary Data . . . . . . . . . . . . . . . . . . . . . . . . . Monitoring of Code Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scrambler / Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command/Indication Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Machine for Activation and Deactivation . . . . . . . . . . . . . . . . . . . State Machine Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Awake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT State Machine (IEC-T / NTC-T Compatible) . . . . . . . . . . . . . . . . Inputs to the U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outputs of the U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT-States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Coding, Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S/Q Channels, Multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transfer between IOM-2 and S0 . . . . . . . . . . . . . . . . . . . . . . . . . Loopback 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layer 1 Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generation of 4B3T Signal Elements . . . . . . . . . . . . . . . . . . . . . . . . . . Complete Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . . . Complete Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 14 15 15 19 19 20 21 21 22 23 23 24 26 27 29 30 33 33 34 35 35 35 38 42 42 42 45 46 47
2001-11-12
PEF 80902
Table of Contents 3.1.5 3.2 3.2.1 3.2.1.1 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 4 4.1 4.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 4.6.3 5 6 6.1 6.1.1 6.1.2 6.2 6.2.1 6.2.2 6.2.3 6.3 7
Page 48 49 49 49 50 50 50 52 55 55 56 56 57 59 59 59 61 62 64 65
Activation Procedures with Loopback #2 . . . . . . . . . . . . . . . . . . . . . . . . Layer 1 Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loopback No.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Complete Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Blocking Recommendation . . . . . . . . . . . . . . . . . . . . . . . U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Appendix: Differences between Q- and T-SMINTO . . . . . . . . . . . . . . . Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Pin ACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Interface Conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Transceiver State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command/Indication Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 68 68 68 69 69 70 72 73
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Data Sheet
2001-11-12
PEF 80902
List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31
Page
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application Example T-SMINTO: Standard NT1 . . . . . . . . . . . . . . . . . 12 IOM-2 Frame Structure of the T-SMINTO . . . . . . . . . . . . . . . . . . . . 14 State Diagram Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Awake Procedure initiated by the LT . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Awake Procedure initiated by the NT. . . . . . . . . . . . . . . . . . . . . . . . . . 24 NT State Machine (IEC-T/NTC-T Compatible). . . . . . . . . . . . . . . . . . . 26 S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . 34 State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Deactivation (always Initiated by LT) . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Activation of Loopback #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Test Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Power Supply Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 External Circuitry U-Transceiver with External Hybrid . . . . . . . . . . . . . 51 External Circuitry S-Interface Transmitter . . . . . . . . . . . . . . . . . . . . . . 54 External Circuitry S-Interface Receiver . . . . . . . . . . . . . . . . . . . . . . . . 54 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Maximum Sinusoidal Ripple on Supply Voltage . . . . . . . . . . . . . . . . 60 Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . . 61 IOM(R)-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . . . . 62 IOM-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . . . . . 62 Reset Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Undervoltage Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 NTC-Q Compatible State Machine Q-SMINTO: 2B1Q . . . . . . . . . . . . 70 IEC-T/NTC-T Compatible State Machine T-SMINTO: 4B3T . . . . . . . . 71 External Circuitry Q- and T-SMINTO . . . . . . . . . . . . . . . . . . . . . . . . . 73
Data Sheet
2001-11-12
PEF 80902
List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33
Page
NT Products of the 2nd Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ACT States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 LP2I States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Frame Structure A for Downstream Transmission LT to NT . . . . . . . . 16 Frame Structure B for Upstream Transmission NT to LT. . . . . . . . . . . 18 MMS 43 Coding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4B3T Decoding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Differences to the former NT-SM of the IEC-T/NTC-T . . . . . . . . . . . . . 27 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Active States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 M Symbol Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Signal Output on Uk0 in State Test . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 C/I-Code Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4B3T Signal Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Generation of the 4B3T Signal Elements. . . . . . . . . . . . . . . . . . . . . . . 43 S/T-Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 U-Transformer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 S-Transformer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Maximum Input Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 S-Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 U-Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Reset Input Signal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Parameters of the UVD/POR Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ACT States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Related Documents to the U-Interface. . . . . . . . . . . . . . . . . . . . . . . . . 69 C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Dimensions of External Components. . . . . . . . . . . . . . . . . . . . . . . . . . 73
Data Sheet
2001-11-12
PEF 80902
Overview
1
Overview
The PEB 80902 (T-SMINTaO) offers all NT1 features known from the PEB 8090 [9] and can hence replace the latter in all NT1 applications. Table 1 on Page 1 summarizes the 2nd generation NT products.
*
Table 1
NT Products of the 2nd Generation PEF 80902 T-SMINT(R)O PEF 81902 T-SMINT(R)IX P-MQFP-64 P-TQFP-64 U+S+HDLC+ IOMa-2 PEF 82902 T-SMINT(R)I P-MQFP-64 P-TQFP-64 U+S+IOMa-2
Package Register access Access via MCLK, watchdog timer, SDS, BCL, Dchannel arbitration, IOMa-2 access and manipulation etc. provided HDLC controller NT1 mode available
P-MQFP-44 no n.a no
parallel (or SCI or IOMa-2) parallel (or SCI or IOMa-2) yes yes
no yes (only)
yes no
no no
Data Sheet
1
2001-11-12
PEF 80902
Overview
1.1
[1] [2] [3]
References
TS 102 080, Transmission and Multiplexing; ISDN basic rate access; Digital transmission system on metallic local lines, ETSI, November 1998 FTZ 1 TR 220 Technische Richtlinie, Spezifikation der ISDN Schnittstelle Uk0 Schicht 1, Deutsche Telecom AG, August 1991 TS 0284/96 Technische Spezifikation Intelligenter Netzabschlu (iNT) mit den Funktionen eines Terminaladapters TA 2a/b (ohne Internverkehr), Deutsche Telekom AG, Marz 2001 pr ETS 300 012 Draft, ISDN; Basic User Network Interface (UNI), ETSI, November 1996 T1.605-1991, ISDN-Basic Access Interface for S and T Reference Points (Layer 1 Specification), ANSI, 1991 I.430, ISDN User-Network Interfaces: Layer 1 Recommendations, ITU, November 1988 IEC-T, ISDN Echocancellation Circuit, PEB 20901 (IEC - TD) / PEB 20902 (IEC - TA), preliminary Target Specification 11.88, Siemens AG, 1988 SBCX, S/T Bus Interface Circuit Extended, PEB 2081 V3.4, User's Manual 11.96, Siemens AG, 1996 NTC-T, Network Termination Controller (4B3T), PEB 8090 V1.1, Data Sheet 06.98, Siemens AG, 1998 INTC-Q, Intelligent Network Termination Controller (2B1Q), PEB 8191 V1.1, Data Sheet 10.97, Siemens AG, 1997 Q-SMINTO, 2B1Q Second Gen. Modular ISDN NT (Ordinary), PEF 80912 Q-SMINTIX, 2B1Q Second Gen. Modular ISDN NT (Intelligent eXended), PEF 81912 Q-SMINTI, 2B1Q Second Gen. Modular ISDN NT (Intelligent), PEF 82912 V1.3, Data Sheets 03.01, Infineon AG, 2001 IOMa-2 Interface Reference Guide, Siemens AG, 03.91 SCOUT-S(X), Siemens Codec with S/T-Transceiver, PSB 2138x V1.1, Preliminary Data Sheet 08.98, Infineon Technologies AG, 1999 PITA, PCI Interface for Telephony/Data Applications V0.3, SICAN GmbH, September1997 Dual Channel SLICOFI-2, HV-SLIC; DUSLIC; PEB3265, 4265, 4266; Data Sheet DS2, Infineon Technologies, July 2000.
[4] [5] [6] [7] [8] [9] [10] [11]
[12] [13] [14] [15]
Data Sheet
2
2001-11-12
4B3T Second Gen. Modular ISDN NT (Ordinary) T-SMINT(R)O
PEF 80902
Version 1.1
CMOS
1.2
Features
Features known from the PEB 8090 * * * * Single chip solution including U- and S-transceiver Perfectly suited for the NT1 in the ISDN Fully automatic activation and deactivation U-interface (4B3T) conform to ETSI [1] and FTZ [2]: - Meets all transmission requirements on all ETSI P-MQFP-44-2 and FTZ loops with margin S/T-interface conform to ETSI [4], ANSI [5] and ITU [6] - Supports point-to-point and bus configurations - Meets and exceeds all transmission requirements Optional IOMa-2 interface eases chip testing and evaluation Power-on reset and Undervoltage Detection with no external components ESD robustness 2kV
*
*
* * *
Type PEF 80902
Data Sheet 3
Package P-MQFP-44
2001-11-12
PEF 80902
Overview New Features * Optional use of transformers with non-negligible resistance corresponding to up to 20 on the line sidePin Vref and the according external capacitor removed * Inputs accept 3.3V and 5V * I/O (open drain) accepts pull-up to 3.3V1) * Pin compatible with Q-SMINTaO (2nd Generation) * LEDs indicating Loopback 2 and activation status * Lowest power consumption due to - Low power CMOS technology (0.35) - Newly optimized low power libraries - High output swing on U- and S-line interface leads to minimized power consumption - Single 3.3 Volt power supply * 185mW (NTC-T: 233mW) power consumption with random data over ETSI Loop 2. * 15mW typical power consumption in power down (as NTC-T; NTC-Q: 28mW)
1.3
Not Supported are ...
* No integrated hybrid is provided by the T-SMINTaO. Therefore, an external hybrid is always required, which consists of only two additional resistors as compared to an integrated hybrid, but allows for more flexibility in board design. * Auxiliary IOMa-2 interface * SRA (capacitive receiver coupling is not suited for S-feeding) * NT-Star with star point on the IOM(R)-2 bus (already not supported in NTC-T).
1)
Pull-ups to 5V must be avoided. A so-called 'hot-electron-effect' would lead to long term degradation.
Data Sheet
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PEF 80902
Overview
1.4
*
Pin Configuration
VDDa_SX VSSa_SX SX2
/LP2I DU
SR2 SR1
SX1
TP1
33 32 31 30 29
28 27 26
25 24 23 22 21 20
/VDDDET TP2 VDDa_SR VSSa_SR XOUT XIN BOUT VDDa_UX VSSa_UX AOUT
34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11
DD
FSC DCL VSSD VDDD BUS
T-SMINTO PEF 80902
19 18 17 16 15 14 13 12
TM2 TM1 TM0 /ACT
VSSa_UR VDDa_UR
/RSTO DIO VDDD
VSSD
AIN BIN
/RST
pin_2.vsd
Figure 1
Pin Configuration
Data Sheet
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PEF 80902
Overview
1.5
*
Block Diagram
XIN SR1 SR2
XOUT
VDDDET
RST RSTO
Clock Generation
POR/UVD
AOUT BOUT
SX1 SX2 S-Transceiver U-Tansceiver AIN BIN
TM0 TM1 TM2
Factory Test Test Modes LED
TP1 TP2 ACT LP2I
DIO
IOM-2 Interface
S Transceiver Control
FSC
DCL
DU
DD
BUS
block diagram.vsd
Figure 2
Block Diagram
Data Sheet
6
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PEF 80902
Overview
1.6
*
Pin Definitions and Functions
Table 2 Pin 2 1 42 43 36 37 31 30 19 20 8 9 22 21
Pin Definitions and Functions Symbol
VDDa_UR
Type - - - - - - - - - - - - O O
Function Supply voltage for U-Receiver (3.3 V 5 %) Analog ground (0 V) U-Receiver Supply voltage for U-Transmitter (3.3 V 5 %) Analog ground (0 V) U-Transmitter Supply voltage for S-Receiver (3.3 V 5 %) Analog ground (0 V) S-Receiver Supply voltage for S-Transmitter (3.3 V 5 %) Analog ground (0 V) S-Transmitter Supply voltage digital circuits (3.3 V 5 %) Ground (0 V) digital circuits Supply voltage digital circuits (3.3 V 5 %) Ground (0 V) digital circuits Frame Sync: 8-kHz frame synchronization signal Data Clock: IOMa-2 interface clock signal (double clock): 512 kHz Loopback 2 indication: Can directly drive a LED (4mA). 0: Loopback 2 closed 1: Loopback 2 not closed. Data Downstream: Data on the IOMa-2 interface
VSSa_UR VDDa_UX
VSSa_UX VDDa_SR
VSSa_SR VDDa_SX
VSSa_SX VDDD
VSSD VDDD
VSSD
FSC DCL
25
LP2I
O
23
DD
I/O
Data Sheet
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2001-11-12
PEF 80902
Overview Table 2 Pin 24 Pin Definitions and Functions (cont'd) Symbol DU Type I/O Function Data Upstream: Data on the IOMa-2 interface Disable IOMa-2: 1: FSC, DCL, DU and DD high Z 0: FSC, DCL, DU and DD push-pull Bus mode on S-interface: 1: passive S-bus (fixed timing) 0: point-to-point / extended passive S-bus (adaptive timing) Reset: Low active reset input. Schmitt-Trigger input with hysteresis of typical 360mV. Tie to '1' if not used. Reset Output: Low active reset output. Test Mode 0. Selects test pattern (see Page 10). Test Mode 1. Selects test pattern (see Page 10). Test Mode 2. Selects test pattern (see Page 10). S-Bus Transmitter Output (positive) S-Bus Transmitter Output (negative) S-Bus Receiver Input S-Bus Receiver Input Crystal 1: Connected to a 15.36 MHz crystal Crystal 2: Connected to a 15.36 MHz crystal
7
DIO
I
18
BUS
I (PU)
5
RST
I
6 13 14 15
RSTO TM0 TM1 TM2
OD I I I
28 29 32 33 40 39
SX1 SX2 SR1 SR2 XIN XOUT
O O I I I O
Data Sheet
8
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PEF 80902
Overview Table 2 Pin 44 41 3 4 34 Pin Definitions and Functions (cont'd) Symbol AOUT BOUT AIN BIN
VDDDET
Type O O I I I
Function Differential U-interface Output Differential U-interface Output Differential U-interface Input Differential U-interface Input VDD Detection: This pin selects if the VDD detection is active ('0') and reset pulses are generated on pin RSTO or whether it is deactivated ('1') and an external reset has to be applied on pin RST. Activation LED. Indicates the activation status of U- and Stransceiver. Can directly drive a LED (4mA). Test Pin 1. Used for factory device test. Tie to 'VSS' Test Pin 2. Used for factory device test. Tie to 'VSS' Tie to `1`
12
ACT
O
27
TP1
I
35
TP2
I
10,11, 16,17, 26,38
PU: Internal pull-up resistor (typ. 100A) I: Input O: Output (Push-Pull) OD: Output (Open Drain)
1.6.1
Specific Pins and Test Modes
LED Pins ACT, LP2I A LED can be connected to pin ACT to display four different states (off, slow flashing, fast flashing, on). It displays the activation status of the U- and S-transceiver according to Table 3.
*
Data Sheet
9
2001-11-12
PEF 80902
Overview Table 3 Pin ACT VDD ACT States LED OFF U_Deactivated 1 0 0 U_Activated x 0 1 1 S_Activated x x 0 1
2Hz (1 : 1)* fast flashing GND ON
1Hz (3 : 1)* slow flashing 0
Note: * denotes the duty cycle 'high' : 'low'. with: U_Deactivated: 'Deactivated State' as defined in Chapter 2.3.7.6. U_Activated: 'SBC Synchronizing', 'Wait for Info U4H', and `Transparent` as defined in Chapter 2.3.7.6. S-Activated: 'Activated State' as defined in Chapter 2.4.5.1. Note: Optionally, pin ACT can drive a second LED with inverse polarity (connect this additional LED to 3.3V only). Another LED can be connected to pin LP2I to indicate an active Loopback 2 according to Table 4. Table 4 Pin LP2I VDD GND LP2I States LED off on Loopback 2 command in the CL -channel received no loopback 2 command or loopback deactivation after a loopback 2 command. Loopback 2 command has been received. Complete analog loop is being closed on the S-interface.
Test Modes Different test patterns on the U- and S-interface can be generated via pins TM0-2 according to Table 5. Table 5 TM0 0 0 0 0
Data Sheet
Test Modes TM1 0 0 1 1 TM2 0 1 0 1
10
U-transceiver
S-transceiver
Reserved for future use. Normal operation in this version. Normal operation 96 kHz1) Continuous Pulses 2 kHz2) Single Pulses
2001-11-12
PEF 80902
Overview Table 5 TM0 1 1 1 1
1) 2) 3) 4)
Test Modes (cont'd) TM1 0 0 1 1 TM2 0 1 0 1 U-transceiver Data Through3) Send Single Pulses Quiet Mode5) normal operation
4)
S-transceiver Normal operation
The S-transceiver transmits pulses with alternating polarity at a rate of 192 kHz resulting in a 96 kHz envelope. The S-transceiver transmits pulses with alternating polarity at a rate of 4 kHz resulting in a 2 kHz envelope. Forces the U-transceiver into the state 'Transparent' where it transmits signal U5. Forces the U-transceiver to go into state 'Test' and to send single pulses. The pulses are issued at 1.0 ms intervals and have a duration of 8.33 s. The U-transceiver is hardware reset.
5)
1.7
System Integration
The T-SMINTaO provides NT1 functionality without a microcontroller being necessary. Special selections can be done via pin strapping (DIO, BUS, TM0-2). The device has no P interface. The IOMa-2 Interface serves only for monitoring and debugging purposes. It can be regarded as a window to the internal IOMa-2. .
Data Sheet
11
2001-11-12
PEF 80902
Overview
*
DC/DC-Converter IDCC PEB2023
S/T - Interface
U - Interface
S
T-SMINTO PEF80902
U
IOM-2
LEDs
Pin Strap - Mode Selection
- Loop 2 Ind. - Activation Status
- Disable IOM - 2 - P - to - P / Bus Selection - Test Pattern Selection
NT1_appl.vsd
Figure 3
Application Example T-SMINTaO: Standard NT1
Data Sheet
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2001-11-12
PEF 80902
Functional Description
2
2.1
Functional Description
Reset Generation
External Reset Input At the RST input an external reset can be applied forcing the T-SMINTaO in the reset state. This external reset signal is additionally fed to the RSTO output. Reset Ouput If VDDDET is active, then the deactivation of a reset output on RSTO is delayed by tDEACT (see Table 28). Reset Generation The T-SMINTaO has an on-chip reset generator based on a Power-On Reset (POR) and Under Voltage Detection (UVD) circuit (see Table 28). The POR/UVD requires no external components. The POR/UVD circuit can be disabled via pin VDDDET. The requirements on VDD ramp-up during power-on reset are described in Chapter 4.6.3. Clocks and Data Lines During Reset During reset the data clock (DCL) and the frame synchronization (FSC) keep running. During reset DD and DU are high; with the exception of: * The output C/I code from the U-Transceiver on DD is 'DR' = 0000 * The output C/I code from the S-Transceiver on DU is 'TIM' = 0000.
Data Sheet
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PEF 80902
Functional Description
2.2
IOM-2 Interface
The IOMa-2 interface always operates in NT mode according to the IOMa-2 Reference Guide [12].
2.2.1
IOMa-2 Functional Description
The IOMa-2 interface consists of four lines: FSC, DCL, DD, DU. The rising edge of FSC indicates the start of an IOMa-2 frame. The DCL clock signal synchronizes the data transfer on both data lines DU and DD. The DCL is twice the bit rate. The bits are shifted out with the rising edge of the first DCL clock cycle. Note: It is not possible to write any data via IOMa-2 into the T-SMINTaO. The IOMa-2 interface can be enabled/disabled with pin DIO. The FSC signal is an 8 kHz frame sync signal. The number of PCM timeslots on the transmit line is determined by the frequency of the DCL clock , with the 512 kHz clock 1 channel consisting of 4 timeslots is available. IOM(R)-2 Frame Structure of the T-SMINTaO The frame structure on the IOMa-2 data ports (DU,DD) of the T-SMINTaO with a DCL clock of 512 kHz is shown in Figure 4.
*
macro_19_QSMINTO
Figure 4
IOM-2 Frame Structure of the T-SMINTaO
The frame is composed of one channel: * Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR programming channel (not available in T-SMINTaO) and a command/indication channel (CI0) for control of e.g. the U-transceiver.
Data Sheet 14 2001-11-12
PEF 80902
Functional Description
2.3
U-Transceiver
The statemachine of the U-Transceiver is compatible to the NT state machine in the PEB 8090 documentation [9], but includes some minor changes for simplification and compliance to Ref. [1]. Basic configurations are selected via pin strapping
2.3.1
4B3T Frame Structure
The 4B3T U-interface performs full duplex data transmission and reception at the Ureference point according to ETSI TS 102 080 and FTZ 1TR 220. It applies the 4B3T block code together with adaptive echo cancelling and equalization. Transmission performance shall be such, that it meets all ETSI and FTZ test loops with margin. The U-interface is designed for data transmission on twisted pair wires in local telephone loops, with basic access to ISDN and a user bit rate of 144 kbit/s. The following information is transmitted over the twisted pair: * Bidirectional: - B1, B2, D data channels - 120 kHz Symbol clock - 1 kHz Frame - Activation - 1 kbit/s Transparent Channel (M symbol), (not implemented) * From LT to NT side: - Power feeding - Deactivation - Remote control of test loops (M symbol) * From NT to LT side: - Indication of monitored code violations (M symbol) Performance Requirements according to FTZ 1 TR 220 (August 1991): On the U-interface, the following transmission ranges are achieved without additional signal regeneration on the loop (bit error rate 10-7): * with noise: 4.2 km on wires of 0.4 mm diameter and 8 km on 0.6 mm wires * without noise: 5 km on wires of 0.4 mm diameter and 10 km on 0.6 mm wires Note: Typical attenuation of FTZ wires of 0.4 mm diameter is about 7dB/km in contrast to ETSI wires of 0.4 mm with about 8dB/km. The transmission ranges can be doubled by inserting a repeater for signal regeneration. Performance requirements according to ETSI TS 102 080 are met, too. 1 ms frames are transmitted via the U-interface, each consisting of: * 108 symbols: 144 bit scrambled and coded B1 + B2 + D data
Data Sheet 15 2001-11-12
PEF 80902
Functional Description * 11 symbols: Barker code for both symbol and frame synchronization (not scrambled) * 1 symbol: Ternary maintenance symbol (not scrambled) The 108 user data symbols are split into four equally structured groups. Each group (27 ternary symbols, resp. 36 bits) contains the user data of two IOM(R)-2 frames in the same order (8B + 8B + 2D + 8B + 8B + 2D). Different syncwords are used for each direction: * Downstream from LT to NT * Upstream from NT to LT +++---+--+- -+--+---+++
On the NT side, the transmitted Barker code begins 60 symbols after the received Barker code and vice versa. Table 6 1 D1 13 D1/2 25 D2 37 D3 49 D4 61 D5 73 D6 85 M 97 D7/8 109 D8 2 D1 14 D1/2 26 D2 38 D3 50 D4 62 D5 74 D6 86 D7 98 D8 110 + Frame Structure A for Downstream Transmission LT to NT 3 D1 15 D1/2 27 D2 39 D3 51 D4 63 D5 75 D6 87 D7 99 D8 111 + 4 D1 16 D2 28 D3 40 D3/4 52 D4 64 D5 76 D6 88 D7 100 D8 112 + 5 D1 17 D2 29 D3 41 D3/4 53 D4 65 D5 77 D6 89 D7 101 D8 113 - 6 D1 18 D2 30 D3 42 D3/4 54 D4 66 D5 78 D6 90 D7 102 D8 114 - 7 D1 19 D2 31 D3 43 D4 55 D5 67 D5/6 79 D6 91 D7 103 D8 115 - 8 D1 20 D2 32 D3 44 D4 56 D5 68 D5/6 80 D6 92 D7 104 D8 116 + 9 D1 21 D2 33 D3 45 D4 57 D5 69 D5/6 81 D6 93 D7 105 D8 117 - 10 D1 22 D2 34 D3 46 D4 58 D5 70 D6 82 D7 94 D7 106 D8 118 - 11 D1 23 D2 35 D3 47 D4 59 D5 71 D6 83 D7 95 D7/8 107 D8 119 + 12 D1 24 D2 36 D3 48 D4 60 D5 72 D6 84 D7 96 D7/8 108 D8 120 -
Data Sheet
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PEF 80902
Functional Description D1 ... D8 M +, - Ternary 2B + D data of IOM(R)-2 frames 1 ... 8 Maintenance symbol Syncword
Data Sheet
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PEF 80902
Functional Description
*
Table 7 1 U1 13 U1/2 25 M 37 U3 49 U4 61 U4 73 U5 85 U6 97 U7 109 U8 U1 ... U8 M +, 2 U1 14 U1/2 26 U2 38 U3 50 - 62 U4 74 U5 86 U6 98 U7 110 U8
Frame Structure B for Upstream Transmission NT to LT 3 U1 15 U1/2 27 U2 39 U3 51 + 63 U4 75 U5 87 U6 99 U7 111 U8 4 U1 16 U2 28 U2 40 U3 52 - 64 U4 76 U5 88 U6 100 U7 112 U8 5 U1 17 U2 29 U3 41 U3/4 53 - 65 U4 77 U5 89 U6 101 U7 113 U8 6 U1 18 U2 30 U3 42 U3/4 54 + 66 U4 78 U5 90 U6 102 U7 114 U8 7 U1 19 U2 31 U3 43 U3/4 55 - 67 U5 79 U5/6 91 U6 103 U7 115 U8 8 U1 20 U2 32 U3 44 U4 56 - 68 U5 80 U5/6 92 U6 104 U7 116 U8 9 U1 21 U2 33 U3 45 U4 57 - 69 U5 81 U5/6 93 U6 105 U7 117 U8 10 U1 22 U2 34 U3 46 U4 58 + 70 U5 82 U6 94 U7 106 U7/8 118 U8 11 U1 23 U2 35 U3 47 U4 59 + 71 U5 83 U6 95 U7 107 U7/8 119 U8 12 U1 24 U2 36 U3 48 U4 60 + 72 U5 84 U6 96 U7 108 U7/8 120 U8
Ternary 2B + D data of IOM(R)-2 frames 1... 8 Maintenance symbol Syncword
Data Sheet
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PEF 80902
Functional Description
2.3.2
Maintenance Channel
The 4B3T frame structure provides a 1 kbit/s M(aintenance)-channel for the transfer of remote loopback commands and error indications. Loopback Commands The LT station uses the M-channel to request remote loopbacks. Loopback commands are coded with a series of '0' and '+' symbols. * A continuous series of '+' requests for loopback 2 activation in the NT * A continuous series of '0' requests for deactivation of any loopback The NT station reacts as soon as the pattern has been detected in 8 consecutive symbols. Error Indications The NT U-transceiver reports line code violations via the M-channel to the exchange by setting one M-Bit to '+' polarity. Transparent Messages The exchange of Transparent Messages via the Transparent Channel is not supported by the T-SMINTO.
2.3.3
Coding from Binary to Ternary Data
Each 4 bit block of binary data is coded into 3 ternary symbols of MMS 43 block code according to Table 8. The number of the next column to be used, is given at the right hand side of each block. The left hand signal elements in the table (both ternary and binary) are transmitted first.
*
Table 8 t 0 0 0 0 1 1 1 0 1 1 0 0 1 0 0 1 0 1 1 1 0
MMS 43 Coding Table S1 t 1 1 0 0 1 0 1 0 - - + + 0 + - 0 + - 0 + - + + 0 0 - - + 1 1 1 1 1 1 2 S2 t 0 - - + + 0 + - 0 + - 0 + - + + 0 0 - - + 2 2 2 2 2 2 3 S3 t 0 - - + + 0 + - 0 + - 0 + - + + 0 0 - - + 3 3 3 3 3 3 4 S4 t 0 - - + + 0 - - 0 + - 0 + - + + 0 0 - - - 4 4 4 4 4 4 1
Data Sheet
19
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PEF 80902
Functional Description Table 8 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 0 0 0 MMS 43 Coding Table (cont'd) S1 1 1 0 0 0 1 0 1 0 0 0 + - + + + 0 + 0 + 0 + + + 0 + + + 0 0 + - 0 + + + 2 2 2 2 2 3 3 3 4 S2 0 0 + - + 0 0 - - 0 + 0 + + 0 - 0 + + 0 0 + - - 0 0 - 3 3 3 3 3 1 1 1 1 S3 0 0 + - + 0 0 - - 0 + 0 - - 0 - 0 + + 0 0 + - - 0 0 - 4 4 4 2 2 2 2 2 2 S4 - - 0 - + 0 0 - - - 0 - - - 0 - 0 + 0 - - + - - 0 0 - 2 2 2 3 3 3 3 3 3
2.3.4
Decoding from Ternary to Binary Data
Decoding is done in the reverse manner of coding. The received blocks of 3 ternary symbols are converted into blocks of 4 bits. The decoding algorithm is given in Table 9. As in the encoding table, the left hand symbol of each block (both binary and ternary) is the first bit and the right hand is the last. If a ternary block "0 0 0" is received, it is decoded to binary "0 0 0 0". This pattern usually occurs only during deactivation.
*
Table 9 0 0 0, 0-+ +-0 0 0 +, -+0 0 + +, - + +, -0+ + 0 0, + - +, + + -, +0- + + +,
Data Sheet
4B3T Decoding Table Ternary Block + 0 +, 0-0 0 0 0 --0 -00 --+ 0-- --- +-- -+-
20
Binary Block 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0
2001-11-12
0 0 0 0 0 1 1 1 1 1
PEF 80902
Functional Description Table 9 0 + 0, 0+- + + 0, 00- 4B3T Decoding Table (cont'd) -0- 1 1 1 1 1 1 0 1 1 1 0 1
2.3.4.1
Monitoring of Code Violations
The running digital sum monitor (RDSM) computes the running digital sum from the received ternary symbols by adding the polarity of the received user data (+ 1, 0, -1). At the end of each block, the running digital sum is supposed to reflect the number of the next column in Table 8. A code violation has occurred if the running digital sum is less than one or more than four at the end of a ternary block, or if the ternary block 0 0 0 (three user symbols with zero polarity) is found in the received data. If at the end of a ternary block no error was found, the running digital sum retains its current value. If the counter value is greater than 4, it is set to 4 at the beginning of the next ternary block, if its value is 0 or less, it is set to one. So after a code violation has been detected, the RDSM synchronizes itself within a period depending on the received data pattern. Note there are some transmission errors which do not cause a code violation.
2.3.5
Scrambler
Scrambler / Descrambler
The binary transmit data from the IOM(R)-2 interface is scrambled with a polynomial of 23 bits, before it is sent to the 4B3T coder. The scrambler polynomial is:: z Descrambler The received data (after decoding from ternary to binary) is multiplied with a polynomial of 23 bits in order to recover the original data before it is forwarded to the IOM(R)-2 interface.The descrambler is self synchronized after 23 symbols. The descrambler polynomial is:: z
- 23 - 23
+z
- 18
+1
+z
-5
+1
The scrambling / descrambling process is controlled fully by the T-SMINTO. Hence, no influence can be taken by the user.
Data Sheet
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PEF 80902
Functional Description
2.3.6
Command/Indication Codes
Both commands and indications depend on the data direction. Table 10 presents all defined C/I codes. A new command or indication will be recognized as valid after it has been detected in two successive IOM(R)-2 frames (double last-look criterion). Indications are strictly state orientated. Refer to the state diagrams in the following sections for commands and indications applicable in various states. Table 10 Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
1)
C/I Codes IN TIM - - LTD - SSP DT - AR reserved - - AI RES - DI
1)
OUT DR - - - RSY - - - AR - ARL - AI - AIL DC
C/I code `1010` must not be input to the U-transceiver.
*
AI AIL AR ARL DT
Activation Indication Activation Indication Loop 2 Activation Request Activation Request Local Loop Data Through Mode
DI DR LTD RES RSY
22
Deactivation Indication. Deactivation Request LT Disable Reset Resynchronization Indication
2001-11-12
Data Sheet
PEF 80902
Functional Description DC Deactivation Confirmation SSP TIM Send-Single-Pulses Timing Request
2.3.7 2.3.7.1
State Machine for Activation and Deactivation State Machine Notation
The following state diagram describes all the actions/reactions resulting from any command or detected signal and resulting from the various operating modes. The states with its inputs and outputs are interpreted as shown below:
Transmitted U-Signal State Name C/I Channel Indication (DOUT)
OUT
SM_expl.emf
Figure 5
State Diagram Example
Each state has one or more transitions to other states. These transitions depend on certain conditions which are noted next to the transition lines. These conditions are the only possibility to leave a state. If more conditions have to be fulfilled together, they are put into parentheses with an AND operator (&). If more than one condition leads to the same transition, they are put into parentheses with an OR operator (|). The meaning of a condition may be inverted by the NOT operator (/). Only the described states and transitions exist. At some transitions, an internal timer is started. The start of a timer is indicated by TxS ('x' is the timer number). Transitions that are caused if a timer has expired are labelled by TxE. Some conditions lead to the same target state. To reduce the number of lines and the complexity of the figures, a state named "ANY STATE" acts on behalf of all state.
Data Sheet
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PEF 80902
Functional Description The state machines are designed to cope with all ISDN devices with IOM(R)-2 standard interfaces. Undefined situations are excluded. In any case, the involved devices will enter defined conditions as soon as the line is deactivated.
2.3.7.2
Awake Protocol
For the awake process two signals are defined' U1W' and 'U2W'. Depending on the call direction (up-, downstream) U1W and U2W are interpreted as awake or acknowledge signals (see figures below).
*
12 ms
7 ms LT INFO U2W 2.133 ms INFO U2 (A)
13 ms NT INFO U1W 2.133 ms
ITD06385.vsd
INFO U1A
Figure 6
Awake Procedure initiated by the LT
*
6 ms
7 ms LT INFO U2W 2.133 ms INFO U2 (A)
13 ms NT INFO U1W 2.133 ms INFO U1A
ITD06386.v sd
Figure 7
Awake Procedure initiated by the NT
Data Sheet
24
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PEF 80902
Functional Description Acting as Calling Station After sending the awake signal, the awaking U-transceiver waits for the acknowledge. After 12 ms, the awake signal is repeated, if no acknowledge has been recognized. If an acknowledge signal has been recognized, the U-transceiver waits for its possible repetition (in case of previous coincidence of two awake signals). If no repetition was detected, the U-transceiver starts transmitting U2 with a delay of 7 ms. If such a repetition is detected, the U-transceiver interprets it as an awake signal and behaves like a device awoken by the far end. Acknowledging a Wake-Up Call If a deactivated device detects an awake signal on U, an acknowledge signal is sent out. After that, the U-transceiver waits for a possible repetition of the awake signal (in case the acknowledge hasn't been recognized). If no repetition is found, the awoken U-transceiver starts sending U2 after 7 ms from detecting the awake signal. If a repeated awake signal is found, the procedure in the awoken U-transceiver starts again.
Data Sheet
25
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PEF 80902
Functional Description
2.3.7.3
*
NT State Machine (IEC-T / NTC-T Compatible)
AWR U0 IOM Awaked DC AR T6S U1W Start Awaking Uk0 RSY T6S T6E U0 Awake Signal Sent RSY AWR T13S T13E U0 Ack. Sent / Received RSY AWT AWR (DI & T05E) T12S U1A Synchronizing RSY U2 T05S DT U1 SBC Synchronizing AR / ARL AI U0 LOF (U0 & T12E) T05S U0 Pend. Deactivation DR DI SP / U0 Test DR SSP or LTD ANY STATE RES DI U0 LOF U0 Reset DR T13S U1W Sending Awake-Ack. RSY T13S AWT T6S T05S T05S T05E U0 Deactivating DC AWR TIM AR U0 Deactivated DC U0, DA AWR
DI
U3 Wait for Info U4H AR / ARL U4H
U0 U5 Transparent AI / AIL U0 LOF U0 Loss of Framing RSY
NT_SM_4B3T_cust.emf
Figure 8
NT State Machine (IEC-T/NTC-T Compatible)
Note: The test modes 'Data Through` (DT), `Send Single Pulses` (SSP) and `Quiet Mode` (QM) can be generated via pins TM0-2 according to Table 5.
Data Sheet
26
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PEF 80902
Functional Description
*
Table 11 1.
Differences to the former NT-SM of the IEC-T/NTC-T Change Comment simplifies SM implementation
No. State/ Signal
State 'Deact. split into 3 states Request Rec.' - 'Pend. Deactivation 1' - 'Reset' State - 'Test' State State 'Loss of Framing' new inserted, results in different behavior in state 'Transparent', no return to normal transmission possible after detection of LOF new inserted renamed to state 'Deactivated' renamed to state 'Transparent' Name Duration
2.
compliance to ETSI TS 102 080, corresponds to state NT1.10
3. 4. 5.
C/I-code LTD State 'Power Down' State 'Data Transmission' Timer variables introduced
for consistency reasons to 2B1Q
6.
see Table 12
2.3.7.4
Inputs to the U-Transceiver
C/I-Commands AI Activation Indication The downstream device issues this indication to announce that layer 1 is available. The U-transceiver in turn informs the LT side by transmitting U3. Activation Request The U-transceiver is requested to start the activation process (if not already done) by sending the wake-up signal U1W. Deactivation Indication This indication is used during a deactivation procedure to inform the Utransceiver that it may enter the 'Deactivated' (power-down) state. Data Through Test Mode This unconditional command is used for test purposes only and forces the Utransceiver into state 'Transparent'.
AR
DI
DT
Data Sheet
27
2001-11-12
PEF 80902
Functional Description LTD LT Disable This unconditional command forces the U-transceiver to state 'Test', where it transmits U0. No further action is initiated. Reset Unconditional command which resets the U-transceiver. Send Single Pulses Unconditional command which requests the transmission of single pulses on the U-interface. Timing The U-transceiver is requested to enter state 'IOM Awaked'.
RES SSP
TIM
U-Interface Events U0 U0 detected U0 is recognized after 120 symbols (1ms) with zero level in a row. Detection may last up to 2 ms. U2 detected The U-transceiver detects U2 if continuous binary 0`s are found after descrambling and LOF = 0 for at least 8 subsequent U-frames. U2 is detected after 8 to 9 ms. U4H detected U4H is recognized, if the U-transceiver detects 16 subsequent binary 1's after descrambling. Awake signal (U2W) detected Awake signal (U1W) has been sent out Loss of Framing on U-interface Timer ended, the started timer has expired
U2
U4H
AWR AWT LOF TxE Timers
The start of timers is indicated by TxS, the expiry by TxE. The following table shows which timers are used.
*
Table 12 Timer T05 T6 0.5 6
Timers Duration (ms) Function C/I code recognition Supervises U1W repetition State Pend. Deactivation, Deactivating Start Awaking Uk0
Data Sheet
28
2001-11-12
PEF 80902
Functional Description Table 12 Timer T12 12 Timers (cont'd) Duration (ms) Function Prevents the U-transceiver in state Synchronizing from immediate transition to state 'Pend. Deactivation' if U0 is detected Supervises U2W repetition State Synchronizing
T13
13
Ack. sent / received Sending awake-ack.
2.3.7.5
Outputs of the U-Transceiver
Below the signals and indications are summarized that are issued on IOM(R)-2 (C/I indications) and on the U-interface (predefined U-signals). C/I Indications AI Activation Indication The U-transceiver has established transparency of transmission. The downstream device is requested to establish layer-1 functionality. Activation Indication Loop-back The U-transceiver has established transparency of transmission. The downstream device is requested to establish a loopback #2. Activation Request The downstream device is requested to start the activation procedure. Activation Request Loop-back The U-transceiver has detected a loop-back 2 command in the M-channel and has established transparency of transmission in the direction IOM(R) to Uinterface. The downstream device is requested to start the activation procedure and to establish a loopback #2. Deactivation Confirmation Idle code on the IOM(R)-2 interface. Deactivation Request The U-transceiver has detected a deactivation request command from the LTside for a complete deactivation. The downstream device is requested to start the deactivation procedure. Resynchronizing Indication RSY informs the downstream device that the U-transceiver is not synchronous.
AIL
AR ARL
DC DR
RSY
Data Sheet
29
2001-11-12
PEF 80902
Functional Description Signals on U-Interface The signals U0, U1W, U1A, U1, U3, U5 and SP are transmitted on the U-interface.They are defined in Table 17. Signals on IOM(R)-2 The Data (B+B+D) is set to all '1's in all states besides the states listed in Table 13.
*
Table 13
Active States
SBC Sychronizing Wait for INFO U4H Transparent Dependence of Outputs The M-symbol output in states with valid M-symbol output its value is set according to Table 14
*:
Table 14 RDS Error
M Symbol Output not detected '0' detected '+'
M Symbol Output
*
Table 15 Input
Signal Output on Uk0 in State Test SSP active SP all other except C/I-Code 'DI' U0
Signal Output on Uk0
*
Table 16
C/I-Code Output SBC Synchronizing AR ARL Wait for Info U4H AR ARL Transparent AI AIL
Loopback Command not received received
2.3.7.6
NT-States
In this section each state is described with its function.
Data Sheet
30
2001-11-12
PEF 80902
Functional Description Acknowledge Sent / Receive After having sent the awake signal, the U-transceiver has received the acknowledge wake tone. If being awoken the U-transceiver has sent the acknowledge. In both cases the U-transceiver waits for possible repetition or time-out. Awake Signal Sent The NT has sent out the awake signal U1W and waits now for a response. If the LT does not react in time timer T6 expires and the NT repeats its wake-up call. Deactivated Only in "Deactivated" state the device may enter the power-down mode. Deactivating State Deactivating assures that the C/I-channel code DC is issued four times before entering the 'Deactivated' state. IOM(R) Awaked The U-transceiver is deactivated, but may not enter the power-down mode. Loss of Framing This state is entered on loss of framing (LOF). No signal is transmitted on the U-interface. A receiver-reset is performed by. Note that there is no return to the 'Transparent' state that has been possible before in the former IEC-T based state machine. Pending Deactivation The U-transceiver has received U0. The U-transceiver remains at least 0.5ms in this state before it accepts DI. SBC Synchronizing The NT is now synchronized and indicates this by AR/ARL towards the downstream device. The NT waits for the acknowledge 'AI' from the downstream device. Sending Awake-Ack. On the receipt of the awake signal U2W the U-transceiver responds with the transmission of U1W.
Data Sheet
31
2001-11-12
PEF 80902
Functional Description Start Awaking Uk0 On the receipt of AR in the C/I-channel the U-transceiver sends the awake signal U1W to start an activation. Synchronizing After the successful awake procedure the U-transceiver trains its receiver coefficients until it is able to detect the signals U2. Reset In state 'Reset' a software-reset is performed. Test State "Test" is entered when the unconditional commands TM2-0='SSP' is applied. The test signal SSP is issued as long as pin SSP is active or C/I=SSP is applied. Transparent The transmission line is fully activated. User data is transparently exchanged by U4/U5. Transparent state is entered in the case of a loopback 2. The downstream device is informed by C/I code AI that the transparent state has been reached Note that in contrast to the former IEC-T state machine there is no resynchronization mechanism. Once loss of framing (LOF) has been detected a deactivation is initiated. Wait for Info U4H The NT is synchronized and waits now for the permission (U4H) to go to the 'Transparent' state.
Data Sheet
32
2001-11-12
PEF 80902
Functional Description
2.4
S-Transceiver
The S-Transceiver offers the NT state machine described in the User's Manual V3.4 [8]. The S-transceiver basic configurations are performed via pin strapping.
2.4.1
Line Coding, Frame Structure
Line Coding The following figure illustrates the line code. A binary ONE is represented by no line signal. Binary ZEROs are coded with alternating positive and negative pulses with two exceptions: For the required frame structure a code violation is indicated by two consecutive pulses of the same polarity. These two pulses can be adjacent or separated by binary ONEs. In bus configurations a binary ZERO always overwrites a binary ONE.
*
011
code violation
Figure 9
S/T -Interface Line Code
Frame Structure Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data (B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see Figure 9). In the direction TE NT the frame is transmitted with a two bit offset. For details on the framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the standard frame structure for both directions (NT TE and TE NT) with all framing and maintenance bits.
Data Sheet
33
2001-11-12
PEF 80902
Functional Description
*
Figure 10 -F - L. -D -E - FA -N - B1 - B2 -A -S -M
Frame Structure at Reference Points S and T (ITU I.430) Framing Bit D.C. Balancing Bit D-Channel Data Bit D-Channel Echo Bit Auxiliary Framing Bit B1-Channel Data Bit B2-Channel Data Bit Activation Bit S-Channel Data Bit Multiframing Bit F = (0b) identifies new frame (always positive pulse, always code violation) L. = (0b) number of binary ZEROs sent after the last L. bit was odd Signaling data specified by user E = D received E-bit is equal to transmitted D-bit See section 6.3 in ITU I.430 N = FA User data User data A = (0b) INFO 2 transmitted A = (1b) INFO 4 transmitted S1 channel data (see note below) M = (1b) Start of new multi-frame
Note: The ITU I.430 standard specifies S1 - S5 for optional use.
2.4.2
S/Q Channels, Multiframing
The S/Q channels are not supported.
Data Sheet
34
2001-11-12
PEF 80902
Functional Description
2.4.3
Data Transfer between IOMa-2 and S0
In the state G3 (Activated) the B1, B2 and D bits are transferred transparently from the S/T to the IOMa-2 interface and vice versa. In all other states '1's are transmitted to the IOMa-2 interface.
2.4.4
Loopback 2
C/I commands ARL and AIL close the analog loop as close to the S-interface as possible. ETSI refers to this loop under 'loopback 2'. ETSI requires, that B1, B2 and D channels have the same propagation delay when being looped back. The D-channel Echo bit is set to bin. 0 during an analog loopback (i.e. loopback 2). The loop is transparent. Note: After C/I-code AIL has been recognized by the S-transceiver, zeros are looped back in the B and D-channels (DU) for four frames.
2.4.5
State Machine
The state diagram notation is given in Figure 11. The information contained in the state diagrams are: - - - - - - state name Signal received from the line interface (INFO) Signal transmitted to the line interface (INFO) C/I code received (commands) C/I code transmitted (indications) transition criteria
The transition criteria are grouped into: - C/I commands - Signals received from the line interface (INFOs) - Reset
Data Sheet
35
2001-11-12
PEF 80902
Functional Description
*
OUT
IN
IOM-2 Interface C/I code
Ind. Cmd. S ta te
Unconditional Transition
S/T Interface INFO
ix
ir
macro_17.vsd
Figure 11
State Diagram Notation
As can be seen from the transition criteria, combinations of multiple conditions are possible as well. A "" stands for a logical AND combination. And a "+" indicates a logical OR combination. Test Signals * 2 kHz Single Pulses (TM1) One pulse with a width of one bit period per frame with alternating polarity. * 96 kHz Continuous Pulses (TM2) Continuous pulses with a pulse width of one bit period. Note: The test signals TM1 and TM2 can be generated via pins TM0-2 according to Table 5. Reset States After an active signal on the reset pin RST the S-transceiver state machine is in the reset state. C/I Codes in Reset State In the reset state the C/I code 0000 (TIM) is issued. This state is entered after a hardware reset (RST). C/I Codes in Deactivated State If the S-transceiver is in state `Deactivated` and receives i0, the C/I code 0000 (TIM) is issued until expiration of the 8 ms timer. Otherwise, the C/I code 1111 (DI) is issued. Receive Infos on S/T I0
Data Sheet
INFO 0 detected
36 2001-11-12
PEF 80902
Functional Description I0 I3 I3 Level detected (signal different to I0) INFO 3 detected Any INFO other than INFO 3
Transmit Infos on S/T I0 I2 I4 It INFO 0 INFO 2 INFO 4 Send Single Pulses (TM1). Send Continuous Pulses (TM2).
Data Sheet
37
2001-11-12
PEF 80902
Functional Description
2.4.5.1
*
State Machine NT Mode
RST TIM RES Reset i0 RES Any State * DC DI ARD1) DR ARD1) TIM DR DR
TM1 TIM TM2 Test Mode i it DC * TM1 TM2 Any State
G4 Pend. Deact. i0 i0 (i0*16ms)+32ms DR
G4 Wait for DR i0 * DC DI TIM DR DC
G1 Deactivated ARD1) i0 i0 (i0*8ms) AR DC DR
G1 i0 Detected i0 * ARD1)
AR ARD G2 Pend. Act i2 i3 i3 AID RSY ARD G2 Lost Framing S/T i2 RSY DR RSY RSY G3 Lost Framing U i2 * i3 i3*ARD AI i3*ARD1) i3*AID2) RSY AID2) ARD1) AID2) i3*AID2) ARD1) AI AID DR ARD DR DR
G2 Wait for AID i2 i3
G3 Activated RSY i4 i3
1): 2)
ARD = AR or ARL : AID =AI or AIL
statem_nt_s.vsd
Figure 12
State Machine NT Mode
Note: By setting the Test Mode pins TM0-2 to '010' / '011': Continuous Pulses / Single Pulses, the S-transceiver starts sending the corresponding test signal, but no state transition is invoked.
Data Sheet 38 2001-11-12
PEF 80902
Functional Description G1 Deactivated The S-transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. Activation is possible from the S/T interface and from the IOMa-2 interface. G1 I0 Detected An INFO 0 is detected on the S/T-interface, translated to an "Activation Request" indication in the C/I channel. The S-transceiver is waiting for an AR command, which normally indicates that the transmission line upstream is synchronized. G2 Pending Activation As a result of the ARD command, an INFO 2 is sent on the S/T-interface. INFO 3 is not yet received. In case of ARL command, loop 2 is closed. G2 wait for AID INFO 3 was received, INFO 2 continues to be transmitted while the S-transceiver waits for a "switch-through" command AID from the device upstream. G3 Activated INFO 4 is sent on the S/T-interface as a result of the "switch through" command AID: the B and D-channels are transparent. On the command AIL, loop 2 is closed. G2 Lost Framing S/T This state is reached when the transceiver has lost synchronism in the state G3 activated. G3 Lost Framing U On receiving an RSY command which usually indicates that synchronization has been lost on the transmission line, the S-transceiver transmits INFO 2. G4 Pending Deactivation This state is triggered by a deactivation request DR, and is an unstable state. Indication DI (state "G4 wait for DR") is issued by the transceiver when: either INFO0 is received for a duration of 16 ms or an internal timer of 32 ms expires.
Data Sheet
39
2001-11-12
PEF 80902
Functional Description G4 wait for DR Final state after a deactivation request. The S-transceiver remains in this state until DC is issued. Unconditional States Test Mode TM1 Send Single Pulses Test Mode TM2 Send Continuous Pulses C/I Commands
*
Command Deactivation Request Reset
Abbr. DR RES
Code 0000 0001
Remark Deactivation Request. Initiates a complete deactivation by transmitting INFO 0. Reset of state machine. Transmission of Info0. No reaction to incoming infos. RES is an unconditional command. Send Single Pulses. Send Continuous Pulses. Receiver is not synchronous Activation Request. This command is used to start an activation. Activation request loop. The transceiver is requested to operate an analog loop-back close to the S/T-interface. Activation Indication. Synchronous receiver, i.e. activation completed.
Send Single Pulses Send Continuous Pulses Receiver not Synchronous Activation Request Activation Request Loop Activation Indication
TM1 TM2 RSY AR ARL
0010 0011 0100 1000 1010
AI
1100
Data Sheet
40
2001-11-12
PEF 80902
Functional Description Command Activation Indication Loop Deactivation Confirmation Abbr. AIL DC Code 1110 1111 Remark Activation Indication Loop Deactivation Confirmation. Transfers the transceiver into a deactivated state in which it can be activated from a terminal (detection of INFO 0 enabled). Remark Interim indication during deactivation procedure. Receiver is not synchronous. INFO 0 received from terminal. Activation proceeds. Illegal code violation received. This function has to be enabled in S_CONF0.EN_ICV. Synchronous receiver, i.e. activation completed. Timer (32 ms) expired or INFO 0 received for a duration of 16 ms after deactivation request.
Indication Timing Receiver not Synchronous Activation Request Illegal Code Ciolation Activation Indication Deactivation Indication
Abbr. TIM RSY AR CVR AI DI
Code 0000 0100 1000 1011 1100 1111
*
Data Sheet
41
2001-11-12
PEF 80902
Operational Description
3
3.1 3.1.1
Operational Description
Layer 1 Activation/Deactivation Generation of 4B3T Signal Elements
For control and monitoring purposes of the activation/deactivation progress the following signal elements are defined by TS 102 080 and FTZ 1 TR 220. Table 17 U0 4B3T Signal Elements No signal or deactivation signal that is used in both directions. Downstream, it requests the NT to deactivate. Upstream, the NT acknowledges by U0 that it is deactivated.
U1W, U2W Awake or awake acknowledge signal used in the awake procedure of the U-interface. U2 The LT sends U2 to enable the own echo canceller to adapt the coefficients. By the Barker code the NT at the other end is enabled to synchronize. The detection of U2 is used by the NT as a criterion for synchronization. The M-channel on U may be used to transfer loop commands. While the NT-RP is synchronizing on the received signal, the LT-RP sends out U2A to enable its echo canceller to adapt the coefficients, but sending no Barker code it inhibits the NT to synchronize on the still asynchronous signal. Due to proceeding synchronization, the U-frame may jump from time to time. U2A can not be detected in the NT at the far end. U1A is similar to U1 but without framing information. While the NT synchronizes on the received signal, it sends out U1A to enable its echo canceller to adapt its coefficients, but sends no Barker code to prevent the LT from synchronizing on the still asynchronous signal. Due to proceeding synchronization, the U-frame may jump from time to time. U1A can not be detected by the far-end LT. When synchronized, the NT sends the Barker code and the LT may synchronize itself. U1 indicates additionally that a terminal equipment has not yet activated. Upon receiving U1 the LT indicates the synchronized state by C/I 'UAI' to layer-2. Usually during activation, no U1 signal is detected in the LT because the TE is activated first and U1 changes to U3 before being detected. The M-channel on U may be used to transfer code error indications and 1 kbit/s transparent data.
Data Sheet 42 2001-11-12
U2A
U1A
U1
PEF 80902
Operational Description Table 17 U3 4B3T Signal Elements (cont'd) U3 indicates that the whole link to the TE is synchronous in both directions. On detecting U3 the LT requests the NT by U4H to establish a fully transparent connection. The M-channel on U may be used to transfer code error indications and 1 kbit/s transparent data. U4H U4H requires the NT to go to the 'Transparent' state. On detecting U4H the NT stops sending signal U3 and informs the S-transceiver or a layer-2 device via the system interface. The M-channel on U may be used to transfer loop commands and 1 kbit/s transparent data. U4 U5 U4 transports operational data on B and D channels. The M-channel on U may be used to transfer loop commands and 1 kbit/s transparent data. U5 transports operational data on B and D channels. The M-channel on U may be used to transfer code error indications and 1 kbit/s transparent data. The T-SMINTO sends periodically single pulses once per millisecond on the U-interface. The test mode can be used for pulse mask measurements. Loss of frame, generated by flywheel Generation of the 4B3T Signal Elements symbols (ternary) sync word (tern ary) M sym bol (tern ary) n/a binary data before scram bling n/a
SP
LOF Table 18
Upstream Downstream (NT to LT) (LT to NT)
U1W
U2W
Resulting in a tone of: Frequency: 7.5 kHz Duration: 2.13 ms when sending the wakeup tone is finished, signal AWT is set and ternary "0" is sent scrambled binary data scrambled binary data scrambled binary data
43
16 times + n/a +++++ ++---- ----
U1A U1 U3
Data Sheet
U2A U2
0 yes yes
0 yes yes
0 0 1
2001-11-12
PEF 80902
Operational Description Table 18 Generation of the 4B3T Signal Elements (cont'd) U4H Duration: 1 ms (warranted by state machine) Binary data from the digital interface Ternary continuous "0" single pulses 0 yes yes 1
U5 U0 SP
U4 U0 SP
yes 0
yes 0 n/a
BBD n/a n/a
once "+", n/a 119 times "0" (repeatedl y)
Table 19
S/T-Interface Signals Signals from TE to NT INFO 0 INFO 1 No signal. A continuous signal with the following pattern: Positive ZERO, negative ZERO, six ONEs.
Signals from NT to TE INFO 0 No signal.
INFO 2
Frame with all bits of B, D, and D-echo channels set to binary ZERO. Bit A set to binary ZERO. N and L bits set according to the normal coding rules. INFO 3 Synchronized frames with operational data on B and D-channels.
INFO 4
Frames with operational data on B, D, and D-echo channels. Bit A set to binary ONE.
Data Sheet
44
2001-11-12
PEF 80902
Operational Description
3.1.2
*
Complete Activation Initiated by Exchange
IOMa-2
TE
S/T-Reference Point
NT
U-Reference Point
LT
IOMa-2
DC DI
INFO 0 INFO 0
S0
DC DI
Uk0
U0 U0
DC DI AR
RSY
U2W U0 U1W U0 U1A U2
AR
AR INFO 2 AR INFO 3 AI AR
U1 UAI
U3 U4H AI INFO 4 AI AR8/10 U5 U4
1 ms
UAI
AI
SBCX-X or IPAC-X
DFE-T
actbyLT_TSMINT.vsd
Figure 13
Activation Initiated by Exchange
Note: The LT starts issuing signal U2 before the NT starts issuing U1A. This chronological order is not displayed for clarification.
Data Sheet
45
2001-11-12
PEF 80902
Operational Description
3.1.3
*
Complete Activation Initiated by TE
IOMa-2
TE
S/T-Reference Point
NT
U-Reference Point
LT
IOMa-2
DC DI TIM PU AR8/10
INFO 0 INFO 0
S0
DC DI
Uk0
U0 U0
DC DI
INFO 1 8ms
TIM AR U1W RSY U0 U2W U0 AR
U1A U2 AR RSY AR INFO 2 INFO 0 INFO 3 AI U1
UAI U3 U4H U5 U4
UAI
AI AI INFO 4
1 ms
AI
SBCX-X or IPAC-X DFE-T
actbyTE_TSMINT.vsd
Figure 14
Activation Initiated by TE
Note: The LT starts issuing signal U2 before the NT starts issuing U1A. This chronological order is not displayed for clarification.
Data Sheet
46
2001-11-12
PEF 80902
Operational Description
3.1.4
*
Deactivation
IOMa-2
TE
S/T-Reference Point
NT
U-Reference Point
LT
IOMa-2
AI AR
INFO 4 INFO 3
S0
AI AI
Uk0
U4 U5
AR AI DR
U0 RSY DR DI DC INFO 0 INFO 0 DI DC DR TIM U0
DEAC DI DC
SBCX-X or IPAC-X
DFE-T
deac_TSMINT.vsd
Figure 15
Deactivation (always Initiated by LT)
Data Sheet
47
2001-11-12
PEF 80902
Operational Description
3.1.5
*
Activation Procedures with Loopback #2
NT IOMa-2 AI AR8/10 TE S/T-Reference Point INFO 4 INFO 3 S0 AI AI Uk0 U-Reference Point U4 U5 LT IOMa-2 AR AI
2B+D U4 (M-Bit= 8x '+' ) AIL
LP2I = 0
AR2
2B+D U4 (M-Bit= 8x '0' ) AI
LP2I = 1
AR
2B+D
SBCX-X or IPAC-X
DFE-T
act_loop2_TSMINT.vsd
Figure 16
Activation of Loopback #2
Note: Closing/resolving loop 2 may provoke the S-transceiver to resynchronize. In this case, the following C/I-codes are exchanged immediately on reception of AIL/AI, respectively: DU: 'RSY', DU: 'AI', DD: 'AIL'/'AI'.
Data Sheet
48
2001-11-12
PEF 80902
Operational Description
3.2
Layer 1 Loopbacks
Test loopbacks are specified by the national PTTs in order to facilitate the location of defect systems. Four different loopbacks are defined. The position of each loopback is illustrated in Figure 17.
*
U
S-BUS Loop 2 S-Transceiver
U
IOM(R)-2
Loop 2 U-Transceiver
IOM(R)-2
Loop 1 A U-Transceiver U-Transceiver Loop 1 U-Transceiver
NT IOM(R)-2
Loop 2 Layer-1 Controller U-Transceiver
IOM(R)-2
Repeater (optional)
Exchange
IOM-2
Loop 3 Layer-1 Controller U-Transceiver
PBX or TE
loop_2b1q.emf
Figure 17
Test Loopbacks
Loopbacks #1, #1A and #2 are controlled by the exchange. Loopback #3 is controlled locally on the remote side. All four loopback types are transparent. This means all bits that are looped back will also be passed onwards in the normal manner. Only the data looped back internally is processed; signals on the receive pins are ignored. The propagation delay of actually looped B and D channels data must be identical in all loopbacks.
3.2.1
Loopback No.2
The following loopback type belongs to the loopback-#2 category: * complete loopback (B1,B2,D), in a downstream device Normally loopback #2 is controlled by the exchange. The maintenance channel is used for this purpose.
3.2.1.1
Complete Loopback
When receiving the request for a complete loopback, the U transceiver passes it on to the S-bus transceiver. This is achieved by issuing the C/I-code AIL in the "Transparent" state or C/I = ARL in states different than "Transparent"
Data Sheet
49
2001-11-12
PEF 80902
Operational Description
3.3 3.3.1
*
External Circuitry Power Supply Blocking Recommendation
The following blocking circuitry is suggested.
VDDa_UR VDDa_UX VDDa_SR VDDa_SX VDDD VDDD 100nF
1)
3.3V
100nF
1)
100nF
1)
100nF
1)
100nF
1)
100nF
1)
1F
VSSD VSSD VSSa_SX VSSa_SR VSSa_UX VSSa_UR
1)
GND
These capacitors should be located as near to the pins as possible
blocking_caps_Smint.vsd
Figure 18
Power Supply Blocking
3.3.2
U-Transceiver
The T-SMINTO is connected to the twisted pair via a transformer. Figure 19 shows the recommended external circuitry with external hybrid. The recommended protection circuitry is not displayed.
Data Sheet
50
2001-11-12
PEF 80902
Operational Description
*
AOUT
R3
RT
BIN
R4
RCOMP
n
C >1 Loop
AIN
R4
RCOMP
R3
BOUT
RT
extcirc_U_Q2_exthybrid.emf
Figure 19
External Circuitry U-Transceiver with External Hybrid
U-Transformer Parameters The following table lists parameters of typical U-transformers. Table 20 U-Transformer Parameters Symbol Value n LH 1 : 1.6 7.5 120 30 0.9 1.8 mH H pF Unit
U-Transformer Parameters U-Transformer ratio; Device side : Line side Main inductanc of windings on the line side
Leakage inductance of windings on the line side LS Coupling capacitance between the windings on CK the device side and the windings on the line side DC resistance of the windings on device side DC resistance of the windings on line side RB RL
Data Sheet
51
2001-11-12
PEF 80902
Operational Description Resistors of the External Hybrid R3, R4 and RT R3 = 1.75 k R4 = 1.0 k RT = 25 Resistors RCOMP / RT * Optional use of trafos with non negligible resistance RB, RL requires compensation resistors RCOMP depending on RB and RL: n2 x (2RCOMP + RB) + RL = 20 * Compliance with Return Loss Measurements: n2 x (2RCOMP + 2RT + Rout + RB) + RL = 150 RB, RL : see Table 20 ROUT : see Table 25 15nF Capacitor To achieve optimum performance the 15nF capacitor should be MKT. A Ceramic capacitor is not recommended. Tolerances * Rs: 1% * C = 15nF: 10-20% * LH = 7.5mH: 10% (2) (1)
3.3.3
S-Transceiver
In order to comply to the physical requirements of ITU recommendation I.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (EMC), the S-transceiver needs some additional circuitry.
Data Sheet
52
2001-11-12
PEF 80902
Operational Description S-Transformer Parameters The following Table 21 lists parameters of a typical S-transformer: Table 21 S-Transformer Parameters Symbol Value n LH 2:1 typ. 30 typ. <3 typ. <100 typ. 2.4 typ. 1.4 mH H pF Unit
Transformer Parameters Transformer ratio; Device side : Line side Main inductance of windings on the line side
Leakage inductance of windings on the line side LS Coupling capacitance between the windings on CK the device side and the windings on the line side DC resistance of the windings on device side DC resistance of the windings on line side Transmitter RB RL
The transmitter requires external resistors Rstx = 47 in order to adjust the output voltage to the pulse mask (nominal 750 mV according to ITU I.430, to be tested with the test mode "TM1") on the one hand and in order to meet the output impedance of minimum 20 on the other hand (to be tested with the testmode 'Continuous Pulses') on the other hand. Note: The resistance of the S-transformer must be taken into account when dimensioning the external resistors Rstx. If the transmit path contains additional components (e.g. a choke), then the resistance of these additional components must be taken into account, too.
Data Sheet
53
2001-11-12
PEF 80902
Operational Description
*
47 SX1 20...40 VDD
2:1
GND SX2 47 DC Point
extcirc_S.vsd
Figure 20 Receiver
External Circuitry S-Interface Transmitter
The receiver of the S-transceiver is symmetrical. 10 k overall resistance are recommended in each receive path. It is preferable to split the resistance into two resistors for each line. This allows to place a high resistance between the transformer and the diode protection circuit (required to pass 96 kHz input impedance test of ITU I.430 [6] and ETS 300012-1). The remaining resistance (1.8 k) protects the Stransceiver itself from input current peaks.
*
1k8 SR1 VDD
8k2
2:1
GND SR2 1k8 8k2 DC Point
extcirc_S.vsd
Figure 21
Data Sheet
External Circuitry S-Interface Receiver
54 2001-11-12
PEF 80902
Operational Description
3.3.4
*
Oscillator Circuitry
Figure 22 illustrates the recommended oscillator circuit.
CLD XOUT 15.36 MHz XIN CLD
Figure 22 Table 22 Parameter Frequency
Crystal Oscillator Crystal Parameters Symbol f CL R1 C0 Limit Values 15.36 +/-60 20 20 7 fundamental Unit MHz ppm pF pF
Frequency calibration tolerance Load capacitance Max. resonance resistance Max. shunt capacitance Oscillator mode External Components and Parasitics
The load capacitance CL is computed from the external capacitances CLD, the parasitic capacitances CPar (pin and PCB capacitances to ground and VDD) and the stray capacitance CIO between XIN and XOUT: ( C LD + C Par ) x ( C LD + C Par ) C L = ------------------------------------------------------------------------ + C IO ( C LD + C Par ) + ( C LD + C Par ) For a specific crystal the total load capacitance is predefined, so the equation must be solved for the external capacitances CLD, which is usually the only variable to be determined by the circuit designer. Typical values for the capacitances CLD connected to the crystal are 22 - 33 pF.
3.3.5
General
- low power LEDs
Data Sheet 55 2001-11-12
PEF 80902
Electrical Characteristics
4
4.1
*
Electrical Characteristics
Absolute Maximum Ratings
Symbol Limit Values Unit C C V V
Parameter Ambient temperature under bias Storage temperature Maximum Voltage on VDD ground
TA TSTG
-40 to 85 - 65 to 150 4.2 -0.3 to VDD + 3.3 (max. < 5.5)
VDD Maximum Voltage on any pin with respect to VS
ESD integrity (according EIA/JESD22-A114B (HBM)): 2 kV Note: Stress above those listed here may cause permanent damage to the device. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. Line Overload Protection The T-SMINTaO is compliant to ESD tests according to ANSI / EOS / ESD-S 5.1-1993 (CDM), EIA/JESD22-A114B (HBM) and to Latch-up tests according to JEDEC EIA / JESD78. From these tests the following max. input currents are derived (Table 23):
*
Table 23 Test ESD Latch-up DC
Maximum Input Currents Pulse Width 100 ns 5 ms -Current 1.3 A +/-200 mA 10 mA Remarks 3 repetitions 2 repetitions, respectively
Data Sheet
56
2001-11-12
PEF 80902
Electrical Characteristics
4.2
*
DC Characteristics
VDD/VDDA = 3.3 V +/- 5% ; VSS/VSSA = 0 V; TA = -40 to 85 C Digital Pins All All except DD/DU ACT,LP2I MCLK DD/DU ACT,LP2I MCLK All Parameter Input low voltage Input high voltage Output low voltage Output high voltage Output low voltage Output high voltage (DD/DU push-pull) Input leakage current Input leakage current (internal pull-up) Analog Pins AIN, BIN Input leakage current ILI 30 A 0 V VIN VD
D
Symbol Limit Values min. VIL VIH VOL1 VOH1 VOL2 VOH2 ILI ILIPU 50 2.4 10 10 200 2.4 0.45 -0.3 2.0 max. 0.8 5.25 0.45
Unit V V V V V V A A A
Test Condition
IOL1 = 3.0 mA IOH1 = 3.0 mA IOL2 = 4.0 mA IOH2 = 4.0 mA 0 V VIN VDD 0 V VIN VDD 0 V VIN VDD
Output leakage current ILO
Table 24 Pin SX1,2
S-Transceiver Characteristics Symbol Limit Values min. typ. 2.2 max. 2.31 V VX 2.03 Unit Test Condition RL = 50
Parameter Absolute value of output pulse amplitude (VSX2 - VSX1) S-Transmitter output impedance
SX1,2
ZX ZR
10 0 10 100
34
k k
see 1) see 2)3) VDD = 3.3 V VDD = 0 V
SR1,2 S-Receiver input impedance
Data Sheet
57
2001-11-12
PEF 80902
Electrical Characteristics
1)
Requirement ITU-T I.430, chapter 8.5.1.1a): 'At all times except when transmitting a binary zero, the output impedance , in the frequency range of 2kHz to 1 MHz, shall exceed the impedance indicated by the template in Figure 11. The requirement is applicable with an applied sinusoidal voltage of 100 mV (r.m.s value)' Requirement ITU-T I.430, chapter 8.5.1.1b): 'When transmitting a binary zero, the output impedance shall be > 20 .': Must be met by external circuitry. Requirement ITU-T I.430, chapter 8.5.1.1b), Note: 'The output impedance limit shall apply for a nominal load impedance (resistive) of 50 . The output impedance for each nominal load shall be defined by determining the peak pulse amplitude for loads equal to the nominal value +/- 10%. The peak amplitude shall be defined as the the amplitude at the midpoint of a pulse. The limitation applies for pulses of both polarities.'
2)
3)
Table 25
U-Transceiver Characteristics Limit Values min. typ. max. dB 50 55 23 %3) mV peak k Unit
Receive Path Signal / (noise + total harmonic distortion) 1) 652) DC-level at AD-output Threshold of level detect (measured between AIN and BIN with respect to zero signal) Input impedance AIN/BIN Transmit Path Signal / (noise + total harmonic distortion) 4) 70 Common mode DC-level Offset between AOUT and BOUT Absolute peak voltage for a single +3 or -3 pulse measured between AOUT and BOUT5) Output impedance AOUT/BOUT: Power-up Power-down
1) 2) 3) 4)
45 10
80
dB 1.65 2.5 1.69 35 2.58 V mV V
1.61 2.42
0.8 3
1.5 6

Test conditions: 1.4 Vpp differential sine wave as input on AIN/BIN with long range (low, critical range). Versions PEF 8x913 with enhanced performance of the U-interface are tested with tightened limit values The percentage of the "1 "-values in the PDM-signal. Interpretation and test conditions: The sum of noise and total harmonic distortion, weighted with a low pass filter 0 to 80 kHz, is at least 70 dB below the signal for an evenly distributed but otherwise random sequence of +3, +1, -1, -3. The signal amplitude measured over a period of 1 min. varies less than 1%.
5)
Data Sheet
58
2001-11-12
PEF 80902
Electrical Characteristics
4.3
*
Capacitances
TA = 25 C, 3.3 V 5 % VSSA = 0 V, VSSD = 0 V, fc = 1 MHz, unmeasured pins grounded. Table 26 Parameter Digital pads: Input Capacitance I/O Capacitance Analog pads: Load Capacitance Pin Capacitances Symbol Limit Values Unit min. CIN CI/O CL max. 7 7 3 pF pF pF pin AIN, BIN Remarks
4.4
*
Power Consumption
Power Consumption VDD=3.3 V, VSS=0 V, Inputs at VSS/VDD, no LED connected, 50% bin. zeros, no output loads except SX1,2 (50 1)) Parameter Operational U and S enabled, IOMa-2 off Limit Values min. typ. 185 165 Power Down
1)
Unit Test Condition
max. mW mW mW U: ETSI loop 1 (0 m) U: ETSI Loop 2 (typical line)
15
50 (2 x TR) on the S-bus.
4.5
Supply Voltages
VDDD = + Vdd 5% VDDA = + Vdd 5% The maximum sinusoidal ripple on VDD is specified in the following figure:
Data Sheet
59
2001-11-12
PEF 80902
Electrical Characteristics
*
mV (peak) 200 100 Supply Voltage Ripple
10
60
80
100
Frequency / kHz
ITD04269.vsd
Frequency Ripple
Figure 23
Maximum Sinusoidal Ripple on Supply Voltage
Data Sheet
60
2001-11-12
PEF 80902
Electrical Characteristics
4.6
AC Characteristics
TA = -40 to 85 C, VDD = 3.3 V 5% Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing measurements are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The AC testing input/output waveforms are shown in Figure 24.
*
2.4 2.0 2.0
Test Points
0.8 0.45 0.8
Device Under Test
CLoad=50 pF
ITS00621.vsd
Figure 24
Input/Output Waveform for AC Tests
Parameter All Output Pins Fall time Rise time
Symbol
Limit values Min Max 30 30
Unit ns ns
Data Sheet
61
2001-11-12
PEF 80902
Electrical Characteristics
4.6.1
*
IOM-2 Interface
DCL
t6 DU/DD (Output) t8 DU/DD (Output) bit n bit n+1 first bit last bit
t7
Figure 25
*
IOM(R)-2 Interface - Bit Synchronization Timing
t9
FSC
t10
DCL
t2 t1 t3
Figure 26
*
IOM-2 Interface - Frame Synchronization Timing
Note: At the start and end of a reset period, a frame jump may occur. This results in a DCL and FSC high time of min. 130 ns after this specific event.
Data Sheet
62
2001-11-12
PEF 80902
Electrical Characteristics Parameter IOM(R)-2 Interface DCL period DCL high DCL low Symbol t1 t2 t3 Limit values Min 1875 850 850 Typ 1953 960 960 Max 2035 1105 1105 100 ns ns ns ns Unit
Output data from high impedance to t6 active (FSC high or other than first timeslot) Output data from active to high impedance Output data delay from clock FSC high t7 t8 t9 50% of FSC cycle time 65 130
100 80
ns ns ns
FSC advance to DCL DCL, FSC rise/fall Data out rise/fall (CL = 50 pF, tristate)
t10 t15 t17
195 30 150
ns ns ns
Data Sheet
63
2001-11-12
PEF 80902
Electrical Characteristics
4.6.2
Table 27 Parameter
Reset
Reset Input Signal Characteristics Symbol tRST Limit Values min. typ. max. ms Power On the 4 ms are assumed to be long enough for the oscillator to run correctly After Power On 4 Unit Test Conditions
Length of active low state
2x DCL clock cycles + 400 ns
*
RST tRST
ITD09823.vsd
Figure 27
Reset Input Signal
Data Sheet
64
2001-11-12
PEF 80902
Electrical Characteristics
4.6.3
*
Undervoltage Detection Characteristics
VDD
VDET
VHYS
VDDmin
t
RSTO
tACT
tACT
tDEACT
tDEACT
t
VDDDET.VSD
Figure 28 Table 28
Undervoltage Control Timing Parameters of the UVD/POR Circuit
VDD= 3.3 V 5 %; VSS= 0 V; TA = -40 to 85 C Parameter Detection Threshold Hysteresis Max. rising/falling VDD edge for activation/ deactivation of UVD Max. rising VDD for power-on2) Min. operating voltage VDDmin 1.5
1)
Symbol min. VDET VHys dVDD/dt 2.7 30
Limit Values typ. 2.8 max. 2.92 90 0.1
Unit Test Condition V mV V/s VDD = 3.3 V 5 %
0.1
V/ ms V
Data Sheet
65
2001-11-12
PEF 80902
Electrical Characteristics VDD= 3.3 V 5 %; VSS= 0 V; TA = -40 to 85 C Parameter Delay for activation of RSTO Delay for deactivation of RSTO
1)
Symbol min. tACT tDEACT
Limit Values typ. max. 10 64
Unit Test Condition s ms
The Detection Threshold VDET is far below the specified supply voltage range of analog and digital parts of the (R) T-SMINT . Therefore, the board designer must take into account that a range of voltages is existing, where neither performance and functionality of the T-SMINT(R) are guaranteed, nor a reset is generated. If the integrated Power-On Reset of the T-SMINTO is selected (VDDDET = '0') and the supply voltage VDD is ramped up from 0V to 3.3V +/- 5%, then the T-SMINTO is kept in reset during VDDmin < VDD < VDET + VHys. VDD must be ramped up so slowly that the T-SMINTO leaves the reset state after the oscillator circuit has already finished start-up. The start-up time of the oscillator circuit is typically in the range between 3ms and 12ms.
2)
Data Sheet
66
2001-11-12
PEF 80902
Package Outlines
5
Package Outlines
Plastic Package, P-MQFP-44 (Metric Quad Flat Package)
*
*
Data Sheet
67
2001-11-12
PEF 80902
Appendix: Differences between Q- and T-SMINTO
6
Appendix: Differences between Q- and T-SMINTaO
Especially the pin compatibility between Q- and T-SMINTaO allows for one single PCB design for both series with only some mounting differences. The following chapter summarizes the main differences between the Q- and TSMINTaO.
The Q- and T-SMINTaO have been designed to be as compatible as possible. However, some differences between them are unavoidable due to the different line codes 2B1Q and 4B3T used for data transmission on the Uk0 line.
6.1 6.1.1
*
Pinning Pin Definitions and Functions
Pin Definitions and Functions Q-SMINTaO: 2B1Q Triple-Last-Look (TLL) Metallic Termination Input (MTI) Auto U Activation (AUA) Cold Start Only (CSO) Power Status (primary) (PS1) Power Status (secondary) (PS2) T-SMINTaO: 4B3T Tie to `1` Tie to `1` Tie to `1` Tie to `1` Tie to `1` Tie to `1`
Table 29 Pin MQFP-44 10 11 16 17 38 26
6.1.2
LED Pin ACT
The 4 LED states (off, fast flashing, slow flashing, on), which can be displayed with pin ACT, are slightly different for Q- and T-SMINTaO (see Table 30). Table 30 LED States Q-SMINTaO: 2B1Q off fast flashing VDD 8Hz (1 : 1)* ACT States Pin ACT T-SMINTaO: 4B3T VDD 2Hz (1 : 1)*
Data Sheet
68
2001-11-12
PEF 80902
Appendix: Differences between Q- and T-SMINTO Table 30 LED States Q-SMINTaO: 2B1Q slow flashing on 1Hz (1 : 1)* GND ACT States (cont'd) Pin ACT T-SMINTaO: 4B3T 1Hz (3 : 1)* GND
Note: * denotes the duty cycle 'high' : 'low'.
6.2 6.2.1
*
U-Transceiver U-Interface Conformity
Related Documents to the U-Interface Q-SMINTaO: 2B1Q T-SMINTaO: 4B3T conform to annex B conform to annex A compliant to 10 ms interruptions
Table 31
ETSI: TS 102 080
ANSI: T1.601-1998 (Revision of ANSI T1.6011992) CNET: ST/LAA/ELR/DNP/ 822 RC7355E FTZ-Richtlinie 1 TR 220
conform not required MLT input and decode logic conform conform not required not required not required conform
Data Sheet
69
2001-11-12
PEF 80902
Appendix: Differences between Q- and T-SMINTO
6.2.2
*
U-Transceiver State Machines
T14S
SN0
.
T14E T14S TL
Pending Timing DC
T14S DI
. SN0 Deactivated DC
TIM DI
AR or TL
Any State SSP or C/I= 'SSP'
SP Test DR
.
. SN0 IOM Awaked PU
AR or TL
SN0 Reset Any State Pin-RST or C/I= 'RES' DR
ARL
.
DI DI & NT-AUTO
T1S, T11S
TN
.
T11E T12S
Alerting PU DC
T12S
T1S T11S
. TN Alerting 1 DR
T11E T12S
T1S, T11S
SN1
.
EC-Training AL DC
LSEC or T12E LSUE or T1E
. SN1 EC-Training DC
SN0
SN1
DI
.
EC-Training 1 DR
LSEC or T12E
act=0 SN3 Wait for SF AL DC
BBD1 & SFD
EQ-Training DC
T20S
..
BBD0 & FD
SN3T act=0 Analog Loop Back AR
LSUE or T1E
SN2
.
T20E & BBD0 & SFD
LOF
Wait for SF DC
DI dea=0 LSUE uoa=0 dea=0 LSUE uoa=0 dea=0 LSUE
SN3/SN3T act=1/0 Pend.Deact. S/T DR
LSUE
1)
3)
dea=0
LOF
SN3/SN3T 1) act=0 Synchronized 1 DC
uoa=1
LOF
SN3/SN3T 1) act=0 Synchronized 2 2) AR/ARL
Al
LOF El1
SN3/SN3T 1) act=1 Wait for Act 2) AR/ARL
act=1 act=0
Any State DT or C/I='DT'
LOF El1
act=1 SN3T Transparent 2) AI/AIL
act=1 & Al
uoa=0 dea=0 LSUE Yes
. SN0 Pend Receive Res. T13S EI1
LSU or ( /LOF & T13E ) T7S
SN3/SN3T 1) act=0 Error S/T act=0 2) AR/ARL
LOF
dea=0 uoa=0 LSUE
uoa=1 ?
No
dea=1 LOF
SN3/SN3T act=1/0 3) Pend.Deact. U DC
LSU
1)
T7E & DI
SN0 Receive Reset DR
.
T7S
TL
Figure 29
NTC-Q Compatible State Machine Q-SMINTaO: 2B1Q
Data Sheet
70
2001-11-12
PEF 80902
Appendix: Differences between Q- and T-SMINTO
*
AWR U0 IOM Awaked DC AR T6S U1W Start Awaking Uk0 RSY T6S T6E U0 Awake Signal Sent RSY AWR T13S T13E U0 Ack. Sent / Received RSY (DI & T05E) T12S U1A Synchronizing RSY U2 (U0 & T12E) T05S U0 Pend. Deactivation DR T05S DT U1 SBC Synchronizing AR / ARL AI U0 LOF DI SP / U0 Test DR SSP or LTD ANY STATE RES DI U0 LOF U0 Reset DR AWT AWR T13S U1W Sending Awake-Ack. RSY T13S AWT T6S T05S T05S T05E U0 Deactivating DC AWR TIM AR U0 Deactivated DC U0, DA AWR
DI
U3 Wait for Info U4H AR / ARL U4H
U0 U5 Transparent AI / AIL U0 LOF U0 Loss of Framing RSY
NT_SM_4B3T_cust.emf
Figure 30
IEC-T/NTC-T Compatible State Machine T-SMINTaO: 4B3T
Data Sheet
71
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PEF 80902
Appendix: Differences between Q- and T-SMINTO
6.2.3
Table 32 Code
Command/Indication Codes
C/I Codes Q-SMINTaO: 2B1Q IN OUT DR - - - EI1 - - PU AR - ARL - AI - AIL DC T-SMINTaO: 4B3T IN TIM - - LTD - SSP DT - AR - - - AI RES - DI OUT DR - - - RSY - - - AR - ARL - AI - AIL DC
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
TIM RES - - EI1 SSP DT - AR - ARL - AI - - DI
Data Sheet
72
2001-11-12
PEF 80902
Appendix: Differences between Q- and T-SMINTO
6.3
External Circuitry
The external circuitry of the Q- and T-SMINTaO is equivalent; however, some external components of the U-transceiver hybrid must be dimensioned different for 2B1Q and 4B3T. All information on the external circuitry is preliminary and may be changed in future documents.
*
AOUT
R3
RT
BIN
R4
RCOMP
n
C >1
RPTC
Loop
AIN
R4
RCOMP
RPTC
R3
BOUT
RT
extcirc_U_Q2_exthybrid.emf
Figure 31
External Circuitry Q- and T-SMINTaO
Note: the necessary protection circuitry is not displayed in Figure 31. Table 33 Component Transformer: Ratio Main Inductivity Resistance Resistance Resistance Capacitor C RPTC and RComp
Data Sheet
Dimensions of External Components Q-SMINTaO: 2B1Q 1:2 14.5 mH 1.3 k 1.0 k 9.5 27 nF 2RPTC + 8RComp = 40
73
T-SMINTaO: 4B3T 1:1.6 7.5 mH 1.75 k 1.0 k 25 15 nF n2 x (2RCOMP + RB) + RL = 20
2001-11-12
PEF 80902
Index
7 A
Index
P
Package Outlines 67 Pin Configuration 5 Pin Definitions and Functions 7 Power Consumption 59 Power Supply Blocking 50 Power-On Reset 13, 65
Absolute Maximum Ratings 56
B
Block Diagram 6
C
C/I Codes U-Transceiver 22
R
Reset Generation 13 Input Signal Characteristics 64 Power-On Reset 13, 65 Under Voltage Detection 13, 65
D
DC Characteristics 57 Differences between Q- and T-SMINT 68
S
S/Q Channels 34 Scrambler / Descrambler 21 S-Transceiver Functional Description 33 State Machine, NT 38 Supply Voltages 59 System Integration 11
E
External Circuitry S-Transceiver 52 U-Transceiver 50
F
Features 3
I
IOM(R)-2 Interface AC Characteristics 62 Frame Structure 14 Functional Description 14
T
Test Modes 10
U
U-Interface Hybrid 50 Under Voltage Detection 13, 65 U-Transceiver 4B3T Frame Structure 15 Functional Description 15 State Machine NT 23
L
Layer 1 Activation / Deactivation 42 Loopbacks 49 LED Pins 9 Line Overload Protection 56
M
Maintenance Channel 19
O
Oscillator Circuitry 55
Data Sheet
74
2001-11-12
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